What does the open source instruction set architecture RISC-V mean for storage processing in a data-rich world?
Accessing information fast and efficiently carries an increasing premium in a world of massive data. That’s where RISC-V, the open source standard for reduced instruction set architecture, comes in.
Heavily backed by the major drive manufacturers, RISC-V may sound like just another industry acronym. But similar to NVMe, commentators suggest it has the potential to reconfigure the way that storage is accessed and processed both at the edge and in the core.
What is RISC-V?
RISC-V is a bold attempt to bring open source principles to processor design.
Today, most of the microprocessor chips produced depend on any of several proprietary architectures controlled by a few large companies. But some are trying to change that.
RISC-V is an extendable open-source microprocessor industry standard architecture (ISA). It was developed in 2010 at the Parallel Computing Lab at U.C. Berkeley, alongside unaffiliated volunteers, and received funding in part from Intel, Microsoft, and other industry leaders.
Far from a mere academic exercise, RISC-V was designed first and foremost with practicality in mind. It has already led companies from across tech to reposition as they anticipate the innovations which the ISA’s flexibility allows.
It is also leading them to adjust their strategies in response to the new opportunities RISC-V’s open-source nature provides for themselves and their competitors.
According to RISC-V International CEO Calista Redmond, the ISA offers a “new level of software and hardware freedom,” enabling easier support for a broad range of operating systems, software vendors and tool developers. It also offers something proprietary architectures do not—transparency, alongside freedom from licensing and royalty fees.
RISC-V for Data Storage
RISC-V is meant to be practical, and in an era where edge computing is on the rise, practicality means customizability.
The 2020s will continue to see an explosive growth in storage needs, as a myriad of new devices come online. IDC analysts project the installed base of global storage capacity to grow at 17.8% per year as a result.
This massive generation of data will require innovation in storage technologies. RISC-V’s modularity will allow designers to address three key design constraints by:
- providing bespoke microprocessors that can handle massive capacity computing needs
- increasing power efficiency
- allowing for more transparent and effective security.
Massive Computing
While not the only game in town, HDD remains for now the most prevalent and affordable option for high-capacity storage. At the same time, storage processor design needs to keep up with advances in areal density.
The engineering realities are hard to avoid. At the virtual RISC-V summit in 2020, Seagate CTO John Morris predicted that to reach 50TB capacity, the next generation of HDDs will need a read-write transducer which can fly across the disk at 2.5 meters per second and come to rest with a precise radial tolerance of 2.4 nanometers, all while accommodating for acoustic, mechanical, and external disturbances.
This requires advances in servo algorithms, enabled by real-time processors. These processors need to be carefully crafted for the task at hand; the RISC-V architecture provides a flexible framework that allows one to design the appropriate chips, and to communicate designs with others doing the same.
Power Savings
The same modularity which helps with data processing allows for more power-efficient devices. RISC-V is an extensible architecture, which means that one can add on or remove features to suit individual needs, including power-saving goals.
In fact, RISC-V architecture has been central to the efforts of the Parallel Ultra Low Power Platform, a joint effort between ETH Zurich and the University of Bologna to design power-optimized computing devices, which they hope will eventually be incorporated into everything from accelerometers to vital-sign monitors.
Their RISC-V based platform has already been used by companies such as GreenWaves in its GAP8 processors. Outside of the PULP project, the low-powered Huami Huangshan-2(MHS002) is set to bring RISC-V implementations to wearable devices in 2021.
Of course, storage and low-powered wearable devices differ in important ways. But a prototype chip by Micro Magic Inc has reportedly reached a clock speed of 5 gigahertz while only burning 1 watt of power at 1.1 volts. That’s less than 1% power of Intel’s Xeon, which runs at 3.2 gigahertz.
With such potential for speed and efficiency, it’s no wonder the major drive manufacturers are taking such a strong interest in RISC-V.
Security
As an open-source ISA, RISC-V’s architectural transparency facilitates secure data storage.
“We live in a time of unprecedented growth of enterprise data—and much of this data is in motion”, says Cecil Macgregor, who runs HDD and SDD chip development at Seagate. This has led some companies, Seagate included, to add customized RISC-V cores to their portfolio. Macgregor emphasizes that by “using open security architectures, they will enable more secure movement of data.”
Customizability comes in handy when a chip’s feature set must be carefully designed in order to meet specialized needs. Sometimes performance takes precedence; other times power efficiency or security is more important to the application at hand.
Seagate’s Adoption Of RISC-V
These sorts of tradeoffs are nicely illustrated by two recently developed Seagate RISC-V cores announced by Macgregor and his team.
The first core emphasizes high performance for real-time critical HDD workloads. Seagate claims that this will dramatically increase real-time processing power available for the servo algorithms that are essential to the development of the next generation of HDDs.
This is crucial, as Seagate expects 50TB+ HDDs by 2026. “Introducing RISC-V to storage devices creates an opportunity to implement application-specific computational capabilities that enable massive parallel computational storage solutions” says Seagate CTO John Morris.
The second core is area and power-optimized, and its uses include security-sensitive edge computational operations. This core boasts high configurability—depending on the task at hand, one can produce implementations with more capabilities, or pare back the feature set in order to make the chip smaller and less power hungry.
“We believe that these architectures support many important use cases that include scientific simulation (for example, weather prediction) as well as the learning part of machine learning,” John Morris adds.
Western Digital Embraces RISC-V
Seagate is far from the only player when it comes to RISC-V implementations. In 2017, Western Digital announced its intention to move all of its processors used in HDDs and SDDs to RISC-V.
“We believe that our ability to design custom compute elements around RISC-V and to combine compute functions with storage will allow us to support the increasingly challenging and varied workloads that our customers demand”, explains Richard New, vice president of research at Western Digital. “The RISC-V initiative, along with other open hardware initiatives will serve as a key building block in the open architectures and solutions of tomorrow”.
Western Digital has made good on its promise. It designed RISC-V based SweRV cores in its controller SoCs to interface directly with NAND flash memory.
There are two SweRV cores, the EL2 and the EH2. RISC-V’s flexibility comes into play yet again, as both cores meet specific needs. EL2 is small, low-powered, and customized for state machines and sequencers. EH2 is a dual-threaded core which enables significant IOPS for computationally demanding random read storage operations.
As with Seagate, Western Digital appears to be only in the relatively early stages of its experimentation with open source RISC-V deployments for storage processing.
ARM, RISC-V, and the Future
Not all RISC is open-source; proprietary ARM chips are still a major force in the industry, and here the outlook is uncertain.
In one major development, GPU giant Nvidia announced in September 2020 that it was purchasing ARM. This has put some of Nvidia’s competitors on edge, especially since so many of them use ARM chips themselves. Although Nvidia has promised not to limit the availability of ARM chips to its competitors, residual uneasiness has provided yet another incentive for companies to drift towards RISC-V.
But it’s not an either-or when it comes to RISC vs RISC-V adoption. Interestingly, Nvidia, Intel, and others with a financial stake in proprietary architectures have invested in RISC-V as well. In fact, companies who use proprietary technologies were among those who originally funded the development of the ISA.
This is what we should expect, according to RISC-V International CEO Calista Redmond. In a time of explosive growth in storage needs, it’s only sensible that industry leaders would diversify their portfolio. More than that, however, it is a sign of genuine interest in the possibilities of RISC-V. They’re open to the idea it might, for some tasks, be a genuinely preferable alternative to currently prevalent proprietary ISAs.
“Western Digital, Nvidia, Google, and others have leveraged RISC-V as part of their portfolio. Having that diversity has been something that’s grown over the last 10 years or so. We’ve seen that. It’s not just as a lever to weigh against other alternatives. It’s a genuine interest, whether it’s coming in at a microcontroller level or looking at RISC-V for their new workloads, where they don’t have existing investments already.”
RISC-V International’s CEO Calista Redmond
Moving Storage Technology Forward
RISC-V is already changing chip design. And as companies either utilize the ISA themselves, or react to competitors that do, it will trigger further disruption. The customizability allowed by RISC-V’s modular design opens up new possibilities for efficient, secure, and specialized microprocessors.
As HDD and SSD technologies adapt to meet the rising wave of data storage needs, the flexibility enabled by a transparent open-sourced ISA may provide the industry with just the shared framework it needs to move forward.
For your storage hardware needs, whether in the data center or at the edge, find out how Horizon Technology can help.
Related Resources
- RISC-V | Seagate
- Seagate Designs RISC-V Cores to Power Data Mobility and Trustworthiness
- RISC-V And Marvell Technologies Advances Enable Storage Solutions
- Fueling the Datasphere How RISC-V Enables the Storage Ecosystem
- RISC-V: what is it all about?
- Is RISC-V Ready to Take a Seat Alongside Intel, AMD, and Arm?
- An Insider’s View Of Verifying Custom RISC-V Processor Cores
- RISC-V, the Linux of the chip world, is starting to produce technological breakthroughs
- About RISC-V Foundation
- RISC-V Processor Designs Emerge
- Strategic Innovation: RISC-V at Western Digital
- RISC-V for Next Generation Storage & Compute
